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Features
* ARM7TDMI(R) ARM(R) Thumb(R) Processor Core * * * * * * * * * * * * * * * *
- High-performance 32-bit RISC Architecture - Embedded ICE (In-circuit Emulation) On-chip SDRAM Controller for Embedded ARM7TDMI Multi-layer AMBA TM Architecture Dual Ethernet 10/100 Mbps MAC Interface Two USARTs with Modem Control Lines Industry-standard Serial Peripheral Interface (SPI) Flexible External Bus Interface with Programmable Chip Selects Multi-level Priority, Individually-maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Additional Watchdog Timer Up to 48 General-purpose I/O Pins JTAG Debug Interface Software Development Tools Available for ARM7TDMI Supported by a Wide Range of Ready-to-use Application Software, Including Multitasking Operating System and Networking Functions 2.5V Power Supply for the Core and PLL Pins, 3.3V for Other I/O Pins Available in 208-lead PQFP and in 256-ball PBGA Packages Supports Commercial and Industrial Temperature Range
Smart Internet Appliance Processor (SIAPTM) AT75C140 Advance Information
Description
The AT75C140 Smart Internet Appliance Processor (SIAPTM) is a high-performance processor specially designed for network-enabling consumer and industrial applications, such as printers, fax machines, industrial automation, data acquisition equipment and test equipment. The AT75C140 is built around an ARM7TDMI microcontroller core running at 40 MHz with a dual Ethernet 10/100 Mbps MAC interface. The specific architecture of the AT75C140 delivers unmatched performance for low power consumption. On top of the AT75C140 hardware platform, Atmel provides a special port of the Linux kernel as the proposed operating system with device drivers for the peripherals.
Rev. 2659A-INTAP-09/02
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AT75C140 Pin Configuration
Table 1. AT75C140 Pinout in 208-lead PQFP Package
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal GND GND VDD3V3 GND NC GND NTRST MA_COL MA_CRS MA_TXER MA_TXD0 MA_TXD1 MA_TXD2 MA_TXD3 MA_TXEN VDD3V3 MA_TXCLK GND MA_RXD0 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER MA_RXCLK GND VDD2V5 MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS GND VDD2V5 VDD3V3 MB_TXER MB_TXD0 MB_TXD1 MB_TXD2 GND MB_TXD3 MB_TXEN Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal MB_TXCLK MB_RXD0 MB_RXD1 MB_RXD2 MB_RXD3 MB_RXER MB_RXCLK MB_RXDV MB_MDC VDD3V3 GND MB_MDIO MB_LINK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VDD3V3 GND A13 A14 A15 A16 A17 A18 A19 A20 A21 D0 D1 D2 D3 GND Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Signal D4 VDD3V3 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 VDD2V5 GND D15 VDD3V3 GND NREQ NGNT VDD3V3 GND DCK NCS A10 NRAS NCAS NC NWE DQM0 DQM1 DQM2 GND DQM3 VDD2V5 GND PLL_VDD XREF240 PLL_GND GND XTALOUT XTALIN VDD2V5 Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Signal NCE0 NCE1 NCE2 VDD3V3 NCE3 NWE0 NWE1 NWE2 VDD3V3 GND NWE3 NWR NSOE GND VDD2V5 NWAIT MISO MOSI SPCK NPCSS VDD3V3 GND NRESET FIQ IRQ0 TST GND VDD2V5 NC VDD3V3 GND VDD3V3 TDO TDI TMS TCK PA19 VDD2V5 GND PA12 GND VDD3V3 Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal PA11 PA10 PA9 PA8 PA7 PA6 VDD3V3 NC PA5 PA4 PA3 PA2 PA1 PA0 GND RXDA TXDA NRTSA NCTSA NDTRA NDSRA NDCDA RXDB TXDB GND PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 VDD3V3 DBW32 GND BO256 VDD3V3
Note:
NC: Not connected
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Table 2. AT75C140 Pinout in 256-ball PBGA Package
Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 Signal GND PB9 PB4 PB1 NDSRB NRTSB RXDB NDSRA TXDA PA2 PA3 PA6 PA10 PA13 PA15 PA19 PA22 PA23 TDO NC BO256 PB8 PB7 PB3 PB0 NDTRB TXDB NDCDA NRTSA PA1 PA5 PA7 PA11 VDD3V3 PA16 PA20 TMS TDI NC NC PB10 PA28 Pin C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 Signal DBW32 PB6 PB2 NRIB NCTSB NRIA NCTSA PA0 PA4 PA8 PA12 PA14 PA18 PA21 TCK NC NC PA31 PB11 PA27 PA26 GND PB5 VDD3V3 NDCDB GND NDTRA RXDA VDD3V3 PA9 GND PA17 VDD3V3 PA24 GND PA29 VDD3V3 IRQ1 NC GND GND PA25 Pin E17 E18 E19 E20 F01 F02 F03 F04 F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 J20 K01 K02 K03 K04 K17 K18 Signal PA30 TST IRQ0 NC PB13 PB12 GND VDD3V3 VDD3V3 FIQ NC SPCK MA_COL PB15 PB14 NTRST NRESET NPCSS MOSI MISO MA_TXD0 MA_TXER MA_CRS GND GND NWAIT VDD3V3 NSOE MA_TXEN MA_TXD3 MA_TXD2 MA_TXD1 NWR NWE3 NC NWE2 MA_RXD0 MA_TXCLK NC VDD3V3 NWE1 NWE0 Pin K19 K20 L01 L02 L03 L04 L17 L18 L19 L20 M01 M02 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 R04 R17 R18 R19 R20 Signal NCE3 NCE2 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER VDD3V3 NCE0 VDD2V5 NCE1 MA_RXCLK VDD3V3 MA_RXDV MA_MDC XREF240 PLL_GND XTALOUT XTALIN MA_MDIO MA_LINK MB_COL GND GND DQM3 VDD3V3 PLL_VDD MB_CRS VDD2V5 MB_TXD0 MB_TXD3 NRAS DQM0 DQM1 DQM2 MB_TXER MB_TXD1 MB_TXEN VDD3V3 VDD3V3 A10 NCAS NWE Pin T01 T02 T03 T04 T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 Signal MB_TXD2 MB_TXCLK MB_RXD1 MB_RXER D28 D31 DCLK NCS MB_RXD0 MB_RXD2 MB_RXCLK GND A1 VDD3V3 A8 GND A17 VDD3V3 D3 D7 GND D16 VDD3V3 D22 GND D27 NC D30 MB_RXD3 MB_RXDV NC A0 A4 A7 A11 A14 A18 A22 D2 D6 D10 D14
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Table 2. AT75C140 Pinout in 256-ball PBGA Package (Continued)
Pin V15 V16 V17 V18 V19 V20 W01 W02 W03 W04 Signal NC D19 D23 D26 NC D29 MB_MDC NC NC MB_LINK Pin W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 Signal A5 A9 A12 A15 A19 A21 D1 D5 D9 D12 Pin W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Signal VDD3V3 D17 D20 D24 NREQ NC NC MB_MDIO A2 A3 Pin Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Signal A6 A10 A13 A16 A20 A23 D0 D4 D8 D11 Pin Y15 Y16 Y17 Y18 Y19 Y20 Signal D13 D15 D18 D21 D25 NGNT
Note:
NC: Not connected
Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package
Pin Name in Package Type Block Common Bus 256-ball PBGA A[23:0] D[31:0] NREQ NGNT Synchronous Dynamic Memory Controller DCLK DQM[3:0] NCS A10 NRAS NCAS NWE Static Memory Controller NCE[3:0] NWE[3:0] NSOE NWR NWAIT I/O Port A PA[12:0] PA[19] PA[18:13] PA[31:20] I/O Port B PB[9:0] PB[15:10] 208-lead PQFP A[21:0] D[15:0] NREQ NGNT DCLK DQM[1:0] NCS A10 NRAS NCAS NWE NCE[3:0] NWE[3:0] NSOE NWR NWAIT PA[12:0] PA[19] PB[9:0] General-purpose I/O lines. Multiplexed with peripheral I/Os Function Address Bus Data Bus Bus Request Bus Grant SDRAM Clock SDRAM Byte Masks SDRAM Chip Select SDRAM Auto Precharge Row Address Strobes Column Address Strobes SDRAM Write Enable Chip Select Byte Select/Write Enable Output Enable Memory Block Write Enable Enable Wait States Active Level Low Low Low Low Low Low Low Low Low Low Low
Type Output, TS(1) I/O(2) Input Output Output Output Output Output Output Output Output Output, TS Output Output, TS Output Input I/O
General-purpose I/O lines. Multiplexed with peripheral I/Os
I/O, PD(3) I/O I/O,PD
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Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type Block Timer/Counter 0 256-ball PBGA TCLK0 TIOA0 TIOB0 Timer/Counter 1 TCLK1 TIOA1 TIOB1 Watchdog Serial Peripheral Interface NWDOVF MISO MOSI SPCK NPCSS NPCS1 USART A RXDA TXDA NRTSA NCTSA NDTRA NDSRA NDCDA NRIA USART B RXDB TXDB NRTSB NCTSB NDTRB NDSRB NDCDB NRIB JTAG Interface NTRST TCK TMS TDI TDO 208-lead PQFP TCLK0 TIOA0 TIOB0 TCLK1 TIOA1 TIOB1 NWDOVF MISO MOSI SPCK NPCSS NPCS1 RXDA TXDA NRTSA NCTSA NDTRA NDSRA NDCDA RXDB TXDB NTRST TCK TMS TDI TDO Function Timer 0 External Clock Timer 0 Signal A Timer 0 Signal B Timer 1 External Clock Timer 1 Signal A Timer 1 Signal B Watchdog Overflow Master In/Slave Out Master Out/Slave In Serial Clock Peripheral Chip Select/Slave Select Optional SPI Chip Select 1 Receive Data Transmit Data Ready to Send Clear to Send Data Terminal Ready Data Set Ready Data Carrier Detect Ring Indicator Receive Data Transmit Data Ready to Send Clear to Send Data Terminal Ready Data Set Ready Data Carrier Detect Ring Indicator Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Active Level Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low -
Type Input I/O I/O Input I/O I/O Output I/O I/O I/O I/O Output Input Output Output Input Output Input Input Input, PU(4) Input Output Output Input, PU Output Input, PU Input, PU Input, PU Input Input Input Input Output
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Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type Block MAC A Interface 256-ball PBGA MA_COL MA_CRS MA_TXER MA_TXD[3:0] MA_TXEN MA_TXCLK MA_RXD[3:0] MA_RXER MA_RXCLK MA_RXDV MA_MDC MA_MDIO MA_LINK MAC B Interface MB_COL MB_CRS MB_TXER MB_TXD[3:0] MB_TXEN MB_TXCLK MB_RXD[3:0] MB_RXER MB_RXCLK MB_RXDV MB_MDC MB_MDIO MB_LINK Power GND PLL_GND PLL_VDD VDD2V5 VDD3V3 208-lead PQFP MA_COL MA_CRS MA_TXER MA_TXD[3:0] MA_TXEN MA_TXCLK MA_RXD[3:0] MA_RXER MA_RXCLK MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS MB_TXER MB_TXD[3:0] MB_TXEN MB_TXCLK MB_RXD[3:0] MB_RXER MB_RXCLK MB_RXDV MB_MDC MB_MDIO MB_LINK GND PLL_GND PLL_VDD VDD2V5 VDD3V3 Function MAC A Collision Detect MAC A Carrier Sense MAC A Transmit Error MAC A Transmit Data Bus MAC A Transmit Enable MAC A Transmit Clock MAC A Receive Data Bus MAC A Receive Error MAC A Receive Clock MAC A Receive Data Valid MAC A Management Data Clock MAC A Management Data Bus MAC A Link Interrupt MAC B Collision Detect MAC B Carrier Sense MAC B Transmit Error MAC B Transmit Data Bus MAC B Transmit Enable MAC B Transmit Clock MAC B Receive Data Bus MAC B Receive Error MAC B Receive Clock MAC B Receive Data Valid MAC B Management Data Clock MAC B Management Data Bus MAC B Link Interrupt Ground PLL Ground PLL Power 2.5V Nominal Supply 3.3V Nominal Supply Active Level -
Type Input Input Output, TS Output, TS Output, TS Input Input Input Input Input Output, TS I/O, PD Input Input Input Output, TS Output, TS Output, TS Input Input Input Input Input Output, TS I/O, PD Input Ground Ground Power Power Power
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Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type Block Miscellaneous 256-ball PBGA BO256 DBW32 FIQ/LOWP IRQ0 IRQ1 NRESET TST XREF240 XTALIN XTALOUT Notes: 1. 2. 3. 4. TS: Three-state I/O: Input/Output PD: Internal Pull-down Resistor PU: Internal Pull-up Resistor 208-lead PQFP BO256 DBW32 FIQ/LOWP IRQ0 External Interrupt Requests NRESET TST XREF240 XTALIN XTALOUT Power on Reset Test Mode External PLL loop filter External Crystal Input External Crystal Output Low High Input, PD Input Input Input Input, PD Output Function Package Size Option External Data Bus Width for NCS Fast Interrupt/Low Power Active Level -
Type Input Input Input Input
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Block Diagram
Figure 1. AT75C140 Block Diagram
Dual Ethernet 10/100 Mbps MAC Interface
ASB Reset
Clocks JTAG

SDRAM Controller External Bus Interface
Embedded ICE
SRAM Controller
ARM7TDMI Core
Peripheral Data Controller
AMBA Bridge SPI
Advanced Interrupt Controller
USART A PIO A USART B PIO B Timer/Counter 0 Timer/Counter 1 Watchdog Timer APB Timer/Counter 2
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Application Example
Figure 2. Process Control
Keyboard Screen
Network
Ethernet 10/100 Mbps PHY Ethernet 10/100 Mbps PHY
PC
Dual-port Ethernet 10/100 Mbps MAC Interface ARM7TDMI Core
SDRAM Controller
SDRAM
External Bus Interface

SRAM Controller
Flash
Test Equipment or Industrial Control
USART AT75C140
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Functional Description
ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bit wide and give maximum code density. Instructions operate on 8-bit, 16-bit and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers.
Ethernet MAC
The AT75C140 contains an Ethernet subsystem mainly composed of three independent parts: two identical independent Ethernet MACs and a packet buffer of 32K bytes, connected together with a local bus. The Ethernet MACs exhibit the following features: * * * * * * * * * Support for 10 and 100 Mbps operation Support for full- and half-duplex Standard MII interface Broadcast, multicast and four unicast address filters Automatic CRC generation Automatic zero padding Pause and jamming support Transmit and receive FIFOs Integrated DMA
The local packet buffer is filled/emptied by the MACs' DMA. This memory is used to store the received/transmitted packets temporarily. Its size allows it to hold enough packets to cope with most situations. Should an overflow occur, a part of the external system memory can be used as an overflow buffer to avoid data loss. The main benefit of having a local bus is that the majority of packets can be received from one MAC and transmitted through the other with minor software intervention.
EBI: External Bus Interface
The EBI generates the signals which control access to external memory or memorymapped peripherals. The EBI is fully programmable. The interface to external devices is composed of common address and data buses and separate control lines to allow the connection of static or dynamic devices. The main common features of the EBI are: * * * External memory mapping 32- or 16-bit data bus width Support for both static and SDRAM-type memories
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Various features specific to static memories or SDRAM memories are listed below.
Static Memories Up to four chip select lines Byte write or byte select lines Two different read protocols Programmable wait state generation Programmable data float time SDRAM Memories Byte, half-word and word access supported CAS latency of two clock cycles supported Auto-precharge command Programmable refresh rate Supports two or four internal banks From 256 up to 2048 columns supported From 2048 up to 8192 rows supported
AIC: Advanced Interrupt Controller
The AT75C140 has an 8-level priority interrupt controller. The interrupt controller outputs are connected to the fast interrupt request (NFIQ) and the normal interrupt request (NIRQ) of the ARM7TDMI core. The processor's NFIQ can only be asserted by the external fast interrupt request input (FIQ). The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals or by the external interrupt request line IRQ0. An 8-level priority encoder allows the application to define the priority between the different interrupt sources. Internal sources are programmed to be level sensitive or edge sensitive. External sources can be programmed to be positive- or negative-edge triggered, or low- or high-level sensitive.
PIO: Parallel I/O Controller
The AT75C140 has up to 48 programmable I/O lines. They can all be programmed as inputs or outputs. To optimize the use of available package pins, most of them are multiplexed with external signals of on-chip peripherals. The PIO lines are controlled by two separate and identical PIO controllers called PIOA and PIOB. The PIO controllers enable the generation of an interrupt on input change on each PIO line. Some I/O lines have enough drive capability to power a LED.
USART: Universal Synchronous/ Asynchronous Receiver/ Transmitter
The AT75C140 provides two identical full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: * * * * * * * * Programmable baud rate generator Parity, framing and overrun error detection Line break generation and detection Automatic echo, local loopback and remote loopback channel modes Multi-drop mode: address detection and generation Interrupt generation Four dedicated peripheral data controller channels 6-, 7- and 8-bit character length (9 bits in multi-drop mode)
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SPI: Serial Peripheral Interface
The AT75C140 includes an SPI which provides communication with external devices in master or slave mode. The SPI contains two dedicated peripheral data controller channels and one external chip select which can be connected to up to 2 devices. The data length is programmable from 8 to 16 bits.
Timer/Counter
The AT75C140 features three identical 16-bit timer/counters. They can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. The triple timer/counter block provides three external clock inputs, five internal clock inputs and two multi-purpose signals which can be configured by the user. Each timer drives an internal interrupt signal which can be programmed to generate processor interrupts via the Advanced Interrupt Controller.
Watchdog Timer PDC: Peripheral Data Controller
The AT75C140 is equipped with an internal Watchdog Timer that can be used to prevent system lock-up if the software becomes trapped in a deadlock. The AT75C140 is furnished with a six-channel peripheral data controller (PDC) dedicated to the two on-chip USARTs and the SPI. One PDC channel is connected to the receiver and one to the transmitter of each peripheral requiring a high data throughput. The user interface of a PDC channel is integrated in the memory space of each USART or SPI channel. It contains a 32-bit address pointer register and a 16-bit transfer counter register. When the programmed number of bytes is transferred, an end-of-transfer interrupt is generated by either the corresponding USART or the SPI.
Special Functions
The AT75C140 provides registers which implement the following special functions: * * * * Chip identification Reset status Power management Temperature range selection
Application Software
The AT75C140 is supported by a comprehensive range of software modules. As a result of the widespread use of the ARM7TDMI, a wide range is available directly from Atmel, from Atmel's qualified software partner or from other third parties. The application software modules are OS level. The AT75C140 is supplied with a customized port of the Linux kernel. It features device drivers for all the on-chip peripherals and supports file system usage. It also supports the native TCP/IP facilities which have made Linux a success in Internet applications. This kernel is available in source code under the terms of the Gnu Public License.
Development Tools
The ARM7TDMI is an industry-standard core. It is supported by a comprehensive range of state-of-the-art development tools, including assemblers, C-compilers, source level debuggers and hardware emulators.
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Packaging
The AT75C140 is supplied in a 208-lead PQFP package. This provides the best compromise between external connectivity and cost. An alternative 256-ball PBGA package is also available. It provides the application developer with a larger I/O capability and improved CPU performance. Although this 256-ball PBGA package is primarily dedicated to development, it can also be used in production for systems which require a high level of connectivity. It offers up to 48 general-purpose I/Os and a full-width system bus (24 address bits and 32 data bits).
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Package Details
Figure 3. PQFP Package Drawing
C
C1
For package data, see Table 4, Table 5 and Table 6 below.
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Table 4. PQFP Package Dimensions (mm)
Symbol c c1 L L1 R2 R1 S Tolerances of Form and Position aaa ccc 0.25 0.10 0.13 0.13 0.4 Min 0.11 0.11 0.65 0.15 0.88 1.60 REF 0.3 Nom Max 0.23 0.19 1.03
Table 5. Dimensions specific to 208-lead PQFP Package (mm)
A Max 4.10 A1 Min 0.25 Min 3.20 A2 Nom 3.40 Max 3.60 Min 0.17 b Max 0.27 Min 0.17 b1 Nom 0.20 Max 0.23 D BSC 31.20 D1 BSC 28.00 E BSC 31.20 E1 BSC 28.00 e BSC 0.50 ddd BSC 0.10
Table 6. 208-lead PQFP Package Electrical Characteristics
Body Size 28 x 28 R (m) Min 53 Max 71 Min 1.4 Cs (pF) Max 1.7 Min 0.56 Cm (pF) Max 0.73 Min 6.7 Ls (nH) Max 8.4 Min 3.9 Lm (nH) Max 5.1
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Figure 4. PBGA Package Drawing
b
For package data, see Table 7, Table 8 and Table 9 below.
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Table 7. PBGA Package Dimensions (mm)
Symbol A1 Diameter B aaa bbb ccc ddd eee Min 0.50 0.60 Nom 0.60 0.75 0.30 0.25 0.35 0.30 0.15 Max 0.70 0.90
Table 8. Dimensions depending on Layer Number of the Package Board (mm)
A Layer 2 4 Min 1.92 2.12 Nom 2.13 2.33 Max 2.34 2.56 Min 0.28 0.44 Dim B Nom 0.32 0.52 Max 0.38 0.60
Table 9. Dimensions specific to 256-ball PBGA Package (mm)
D/E e REF 1.27 Body Row Array P4R Min 26.8 Nom 27.0 Max 27.2 Min D1/E1 Nom 24.0 Max 24.7 f REF 8.05 J/L REF 1.44
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
ATMEL (R) is the registered trademark of Atmel; SIAP is a trademark of Atmel. ARM (R), Thumb (R) and ARM Powered(R) are registered trademarks of ARM Ltd.; ARM7TDMI and AMBA are trademarks of ARM Limited. Linux (R) is a registered trademark of Linus Torvalds. Other terms and product names may be the trademarks of others.
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